Semiconductor integrated circuit

ABSTRACT

A semiconductor integrated circuit in which, when leading out multiple-phase clock signal wirings from the ring oscillator circuit capable of oscillating at a high frequency, increase in the area of the substrate and deterioration in the clock phase accuracy caused by the non-uniform stray capacitances among the multiple-phase clock signal wirings are prevented. The semiconductor integrated circuit includes: N-stage amplifying circuits connected in a form of a ring to perform oscillating operation, which amplifying circuits are arranged in a semiconductor substrate to be divided into a plurality of rows, wherein in each row an amplifying circuit of “m−1”th stage and an amplifying circuit of “m”th stage are not adjacent to each other, where m is an arbitrary integer number within a range from 2 to N; and a plurality of wirings for respectively leading out a plurality of output signals from the amplifying circuits disposed in one of the plurality of rows.

TECHNICAL FIELD

[0001] The present invention generally relates to a semiconductorintegrated circuit, and in particular to a semiconductor integratedcircuit including a ring oscillator circuit for generating multi-phaseclock signals.

BACKGROUND ART

[0002] Recently, in the signal transmission between equipments, a systemusing a high-speed serial signal with small amplitude has been adopted.This system makes it possible, as compared with the technique whereinthe digital signal is transmitted in parallel, to reduce electromagneticinterference (EMI) caused in the course of digital signal transmission,in addition to a requirement for only a small number of cables.

[0003] In order to achieve a high-speed serial communication, there isprovided at the transmitting side a parallel-serial conversion circuit,which synchronizes with a base clock signal to convert parallel datainto serial data by using sub clock signals with multi-phases (in thisapplication, referred to as multi-phase clock signals) having a phasedifference of equal intervals. Therefore there arises a need to providea multi-phase clock generating circuit that generates the multi-phaseclock signals and supply the multi-phase clock signals to theparallel-serial conversion circuit.

[0004] As the multi-phase clock generating circuit, there is used, forexample, a voltage or current controlled differential ring oscillatorcircuit, which is constructed of multi-stage delay differentialinverting amplification circuits connected to each other in the form ofa ring. By using the differential ring oscillator circuit as describedabove, multi-phase clock signals having phase difference with equalintervals can be easily extracted from the multi-stage delaydifferential inverting amplification circuits. In order to generate themulti-phase clock signals having phase difference of precisely equalintervals from high-speed differential ring oscillator circuit, it isnecessary to equalize the loads of the multi-stage delay differentialinverting amplification circuits and also to equalize the straycapacitances of the multiple-phase clock signal wirings.

[0005] Conventionally, in order to equalize the load of each stage ofdelay differential inverting amplification circuits, N-stage delaydifferential inverting amplification circuits, which constitutes thedifferential ring oscillator circuit, are disposed in two rows on asemiconductor substrate, and in each row, there is made such anarrangement that the successive delay differential invertingamplification circuits are disposed adjacent to each other. By virtue ofthis arrangement, it is made possible to minimize the delay in thewirings between the output of one circuit and the input of the nextcircuit of the N-stage delay differential inverting amplificationcircuits, and to achieve a differential ring oscillator circuit capableof oscillating at a high frequency.

[0006] However, in the differential ring oscillator circuit that outputsmulti-phase clock signals having phase difference of equal intervals andis required for achieving the high speed serial communication,multi-phase clock signals are generally extracted from the outputs ofthe alternate delay differential inverting amplification circuits.Accordingly, signals are extracted from each row of the delaydifferential inverting amplification circuits disposed in two rows.Consequently, according to the conventional arrangement and wirings, thelength of the wirings for the multi-phase clock signals of one rowbecomes longer than that of another row, and therefore, there arises adifficulty to make uniform all stray capacitances of the multiple-phaseclock signal wirings. Also, the layout of the multiple-phase clocksignal wirings has to be made in a relatively wide area in the peripheryof the differential ring oscillator circuit. For this reason, therearises such problem that the area of the semiconductor substrate becomeslarger.

DISCLOSURE OF THE INVENTION

[0007] Accordingly, in view of the above-mentioned problems, an objectof the present invention is to provide a semiconductor integratedcircuit in which, when leading out or extracting multiple-phase clocksignal wirings from the ring oscillator circuit capable of oscillatingat a high frequency, increase in the area of the substrate anddeterioration in the clock phase accuracy caused by the non-uniformstray capacitances among the multiple-phase clock signal wirings areprevented.

[0008] In order to solve the above-mentioned problems, a semiconductorintegrated circuit according to a first aspect of the present inventioncomprises: N-stage amplifying circuits (N is a natural number) connectedin a form of a ring to perform oscillating operation, which amplifyingcircuits are arranged in a semiconductor substrate to be divided into aplurality of rows, wherein in each row an amplifying circuit of “m−1”thstage and an amplifying circuit of “m”th stage are not adjacent to eachother, where m is an arbitrary integer number within a range from 2 toN; and a plurality of wirings for respectively leading out a pluralityof output signals from the amplifying circuits disposed in one of theplurality of rows.

[0009] Further, a semiconductor integrated circuit according to a secondaspect of the present invention comprises: N-stage amplifying circuitsconnected in a form of a ring to perform oscillating operation to outputM-phase clock signals having equal phase intervals (M and N are naturalnumbers and M≦N) , which amplifying circuits are arranged in asemiconductor substrate to be divided into two rows; and M wirings forrespectively leading out M-phase clock signals from the amplifyingcircuits disposed in one of the two rows.

[0010] According to the present invention, a plurality of wirings areformed such that a plurality of output signals (multi-phase clocksignals) are led out or extracted from one row of N-stage amplifyingcircuits, which are disposed to be divided into a plurality of rows inthe semiconductor substrate. Accordingly, it is made possible toequalize the stray capacitances among the multiple-phase clock signalwirings, and therefore, to prevent increase in the area of the substrateand deterioration in the accuracy in clock phase signal wirings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Advantages and characteristics of the present invention willbecome apparent by considering the following detailed descriptions anddrawings in conjunction. IN those drawings, the same component elementswill be given with the same reference numerals.

[0012]FIG. 1 is a circuit diagram showing a voltage-controlleddifferential ring oscillator circuit included in a semiconductorintegrated circuit according to a first embodiment of the presentinvention;

[0013]FIGS. 2A and 2B are diagrams showing the delay differentialinverting amplification circuits included in the voltage-controlleddifferential ring oscillator circuit as shown in FIG. 1;

[0014]FIG. 3 is a diagram showing voltage waveform of multi-phase clocksignals which are outputted from the delay differential invertingamplification circuits included in the voltage-controlled differentialring oscillator circuit as shown in FIG. 1;

[0015]FIG. 4 is a circuit diagram showing voltage-controlleddifferential ring oscillator circuits and buffer circuits which areincluded in the semiconductor integrated circuit according to the firstembodiment of the present invention;

[0016]FIG. 5 is a diagram showing an example of the layout and wiringsfor leading out multi-phase clock signals from a voltage-controlleddifferential ring oscillator circuit;

[0017]FIG. 6 is a diagram showing the layout and wirings for leading outmulti-phase clock signals from the voltage-controlled differential ringoscillator circuit in the semiconductor integrated circuit according tothe first embodiment of the present invention;

[0018]FIG. 7A is an explanatory diagram for illustrating the layout ofthe delay differential inverting amplification circuits as shown in FIG.6, and FIG. 7B is an explanatory diagram for illustrating the layout ofthe delay differential inverting amplification circuits as shown in FIG.5; and

[0019]FIG. 8 is a diagram for illustrating the layout of delaydifferential inverting amplification circuits included in asemiconductor integrated circuit according to a second embodiment of thepresent invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0020]FIG. 1 is a circuit diagram showing a voltage-controlleddifferential ring oscillator circuit included in a semiconductorintegrated circuit according to a first embodiment of the presentinvention.

[0021] As shown in FIG. 1, a voltage-controlled differential ringoscillator circuit 100 includes N-stage (in this embodiment, 8-stage)delay differential inverting amplification circuits 101 a-101 h andcontrol terminal 102 for controlling the delay time in the delaydifferential inverting amplification circuit of each stage. Connected tothe control terminal 102 is a control voltage source 103.

[0022] As shown in FIG. 2A, the delay differential invertingamplification circuit 101 of each stage has a non-inverting inputterminal 206 and an inverting input terminal 207, and a non-invertingoutput terminal 208 and an inverting output terminal 209. A controlvoltage VC, which is applied to the control voltage input terminal 210,controls the delay time in the delay differential invertingamplification circuit 101. Alternatively, a control current may controlthe delay time in the delay differential inverting amplification circuit101.

[0023]FIG. 2B shows an internal circuit of the delay differentialinverting amplification circuit 101 of each stage. The delaydifferential inverting amplification circuit 101 includes resistors 201and 202 for varying the voltages, MOS transistors 203 and 204, and aconstant current source 205. The delay differential invertingamplification circuit 101 supplies differential signals, which areobtained by amplifying a difference between a signal applied to thenon-inverting input terminal 206 and a signal applied to the invertinginput terminal 207, to the non-inverting output terminal 208 and theinverting output terminal 209. A voltage between a drain and a source ofeach of the MOS transistors 203 and 204 is varied by the control voltageVC applied to the control voltage input terminal 210. As a consequence,the delay time in the delay differential inverting amplification circuit101 is controlled. Although, MOS transistors are used as the amplifyingelements in this embodiment, but the present invention is applicable toa case where amplifying elements other than that is used.

[0024] Referring to FIG. 1 again, the voltage-controlled differentialring oscillator circuit 100 includes 8-stage delay differentialinverting amplification circuits 101 a-101 h connected in the form of aring. The delay differential inverting amplification circuit of eachstage has a differential input terminal pair 104 and a differentialoutput terminal pair 105. The differential output terminal pair 105 ofthe delay differential inverting amplification circuit 101 a of thefirst stage is connected to the differential input terminal pair 104 ofthe delay differential inverting amplification circuit 101 b of thesecond stage, the differential output terminal pair 105 of the delaydifferential inverting amplification circuit 101 b of the second stageis connected to the differential input terminal pair 104 of the delaydifferential inverting amplification circuit 101 c of the third stage,and so on. Thus, finally the differential output terminal pair 105 ofthe delay differential inverting amplification circuit 101 h of the last8th stage is connected to the differential input terminal pair 104 ofthe delay differential inverting amplification circuit 101 a of thefirst stage in the form of cross connection. As a result, 8-stage delaydifferential inverting amplification circuits 101 a-101 h, which areconnected in the form of a ring as described above, produce output clocksignals φ1-φ16 from respective differential output terminal pairs 105.

[0025]FIG. 3 shows voltage waveform of the clock signals φ1-φ16. In FIG.3, the abscissa axis indicates the time, while the ordinate axisindicates the voltage. The delay differential inverting amplificationcircuit of each stage inverts and outputs the signal being delayed by aunit delay time T_(DELAY), which is determined by the applied controlvoltage VC, with respect to the input signal. Here, in the differentialring oscillator circuit constituted of N-stage delay differentialinverting amplification circuits, cycle period T_(CLOCK), which is areciprocal of oscillation frequency, is expressed by the followingformula:

T _(CLOCK)=2×N×T _(DELAY)=16×T _(DELAY)  (1)

[0026] As demonstrated in the formula (1), the cycle period T_(CLOCK) ofthe differential ring oscillator circuit depends on the number of stagesN of the delay differential inverting amplification circuits and theunit delay time T_(DELAY) in each stage. In the differential ringoscillator circuit as described above, in order to obtain a highoscillation frequency when a control voltage leading to minimum delaytime is applied, it is required to design such that the number of stagesof the delay differential inverting amplification circuits is to be atminimum, and the stray capacitances in the output wirings of the delaydifferential inverting amplification circuits is to be small so that theunit delay time T_(DELAY) becomes small.

[0027] By the way, in order to achieve a high-speed serialcommunication, there are required multi-phase clock signals having aphase difference of equal intervals. The number of phases of themulti-phase clock signals depends on the number of serial data whichcorrespond to one parallel data. Generally, multi-phase clock signalshaving 4-10 phases are required. Now, a method will be described ofselecting the multi-phase clock signals having phase difference of equalintervals, which are required for carrying out high-speed serialcommunication, from the clock signals φ1-φ16 as shown in FIG. 3.

[0028] Generally, in order to generate M-phase clock signals,differential ring oscillator circuit having delay differential invertingamplification circuits of N=n×M stages can be used (n is a naturalnumber). However, as previously described, since the minimum value ofthe cycle period T_(CLOCK) in the differential ring oscillator circuitdepends on the number of stages of the delay differential invertingamplification circuits and the unit delay time T_(DELAY) of each stage.Therefore, in order to obtain a high oscillation frequency required forserial communication, it is preferred that the number of stages is atminimum as required. Accordingly, a condition of n=1 is selected,generally. However, the present invention is also applicable to a caseof n>1. In this embodiment, there is adopted a configuration having8-stage delay differential inverting amplification circuits, in which nis 1, i.e., N is M, so as to generate 8-phase clock signals.

[0029] In order to obtain multi-phase clock signals of 8 phases havingphase difference of equal intervals from the clock signals output fromthese delay differential inverting amplification circuits, clock signalsare selected which are different in phase by an amount of the time aslarge as cycle period T_(CLOCK) divided by 8. Referring to FIG. 3, assuch clock signals, the following clock signals are suitable, that is,the clock signals of odd numbers φ1, φ3, φ5, . . . , and φ15 or theclock signals of even numbers φ2, φ4, φ6, . . . , and φ16. In thisembodiment, the clock signals of odd numbers are selected. However, thesame effect can be obtained as well by selecting the clock signals ofeven numbers.

[0030]FIG. 4 is a circuit diagram showing a voltage-controlleddifferential ring oscillator circuit and buffer circuits which areincluded in the semiconductor integrated circuit according to the firstembodiment of the present invention. Here, there are added eight buffercircuits 301 a-301 h for outputting clock signals φ1, φ3, φ5, . . . ,and φ15 of odd numbers as the multi-phase clock signals to thevoltage-controlled differential ring oscillator circuit 100 as shown inFIG. 1.

[0031] To reduce the stray capacitances in the output wirings of thedelay differential inverting amplification circuits, there is a need todesign the layout and wirings such that possible shortest outgoing lines302 a-302 d of the multi-phase clock signals extending from the delaydifferential inverting amplification circuits 101 a-101 h to the buffercircuits 301 a-301 h can be obtained when forming the circuit as shownin FIG. 4 on a semiconductor substrate.

[0032] To achieve the above, the layout and wirings as shown in FIG. 5is conceivable. As shown in FIG. 5, the delay differential invertingamplification circuits 101 a-101 h are disposed in two rows. In eachrow, the delay differential inverting amplification circuits except forthe both ends are disposed adjacent to each other. Further, the buffercircuits 301 a-301 h are disposed close to the delay differentialinverting amplification circuits 101 a-101 h so that the outgoing lines302 a-302 d are as short as possible. By designing the layout andwirings as described above, it is made possible to obtain the minimumlength of the wirings for connecting stages and thereupon equalize andminimize the stray capacitances due to the wirings connecting adjacentstages. However, according to the wirings as described above, thewirings for supplying clock signals φ1, φ3, φ5, . . . , and φ15 from thebuffer circuits 301 a-301 h to a parallel-serial conversion circuit 402are arranged to be divided into the upper side and the lower side of thevoltage-controlled differential ring oscillator circuit 100 and ledabout. As a result, there occurs a great difference between the straycapacitances of the wirings 401 a of the multi-phase clock signalsdisposed at the upper side and the stray capacitances of the wirings 401b of the multi-phase clock signals disposed at the lower side.

[0033] In the high-speed serial communication, it is of importance thatthe precisely equal phases of the multi-phase clock signals areavailable. Accordingly, when wiring the multi-phase clock signals on thesemiconductor substrate, a great care has to be paid to the layout ofthe multiple-phase clock signal wirings on the semiconductor substrate.That is, there has to be equalized electromagnetic/capacitive couplingof the multi-phase clock signals among plural clock signals. Further, asshown in FIG. 5, when multiple-phase clock signal wirings are led aroundin a relatively wide region in the periphery of the voltage-controlleddifferential ring transmitting circuit 100, this region is unable to beused for another purpose. Accordingly, a large area of the semiconductorsubstrate is required.

[0034] Thus, in this embodiment, the layout and wirings as shown in FIG.6 are carried out. As shown in FIG. 6, there are disposed in asemiconductor substrate the voltage-controlled differential ringoscillator circuit 100, buffer circuits 301 a-301 h for the multi-phaseclock signals and the parallel-serial conversion circuit 402. The delaydifferential inverting amplification circuits 10la-101 h, which areconnected in the form of a ring in the voltage-controlled differentialring oscillator circuit 100, are alternately disposed in the first andsecond rows unlike the order of the connection in the circuit. Bydisposing them alternately as described above, it is made possible tolead out or extract multi-phase clock signals from the delaydifferential inverting amplification circuits disposed at only one sideof the first and second rows. In FIG. 6, it suffices to carry out thewirings such that multi-phase clock signals are led out only from thedelay differential inverting amplification circuits 101 a, 101 g, 101 cand 101 e which are disposed at the lower side row. Accordingly, theleader wirings 401 c for multi-phase clock signals can be all collectedat the lower side of the voltage-controlled differential ring oscillatorcircuit 100. By virtue of this arrangement, the stray capacitances ofthe multiple-phase clock signal wirings can be equalized.

[0035]FIG. 7A is an explanatory diagram for illustrating the layout ofthe 8-stage delay differential inverting amplification circuits as shownin FIG. 6; while FIG. 7B is an explanatory diagram for illustrating thelayout of the 8-stage delay differential inverting amplificationcircuits as shown in FIG. 5 for the comparative example. In FIGS. 7A and7B, the numerals #1-#8 given to the delay differential invertingamplification circuits indicate the order of the connection in thecircuit. In the comparative example as shown in FIG. 7B, the order ofthe connection in the circuit agrees with the disposed order thereof. Inthe embodiment as shown in FIG. 7A, the order of the connection in thecircuit disagrees with the disposed order thereof.

[0036] As understood from FIGS. 7A and 7B, the length of the wiringsconnecting the 8-stage delay differential inverting amplificationcircuits in this embodiment is longer than the length of the wirings incomparative example. However, the length of the wirings in theembodiment is approximately the same as the wiring length at the bothends of the rows of the delay differential inverting amplificationcircuits in the comparative example. Accordingly, the high frequencycharacteristics of the voltage-controlled differential ring oscillatorcircuit according to this embodiment are not inferior to those of thevoltage-controlled differential ring oscillator circuit in thecomparative example.

[0037] Next, a second embodiment of the present invention will bedescribed. FIG. 8 is a diagram for illustrating the layout of delaydifferential inverting amplification circuits included in thevoltage-controlled differential ring oscillator circuit within asemiconductor integrated circuit according to the second embodiment ofthe present invention. In this embodiment, the number of stages N of thedelay differential inverting amplification circuits is set to be 10. InFIG. 8, the numerals #1-#10 given to the delay differential invertingamplification circuits indicate the order of the connection in thecircuit.

[0038] As shown in FIG. 8, even when the number of stages of the delaydifferential inverting amplification circuits which are ring-connected,by disposing these delay differential inverting amplification circuitsalternately in a first row and a second row, multi-phase clock signalscan be extracted from the delay differential inverting amplificationcircuits which are disposed in only one of the first and second row.Accordingly, the stray capacitances of the multiple-phase clock signalwirings can be made equal to each other.

[0039] Generally, it may be arranged so that, in a case where N-stagedelay differential inverting amplification circuits are used, as toprovided m=1, 2, . . . , N, an amplifying circuit of the “m”th stage isdisposed at the “m”th position of the first row in the semiconductorsubstrate in a case where m is an odd number equal to or less than N/2,an amplifying circuit of the “m”th stage is disposed at the “N+1−m”thposition of the first row in the semiconductor substrate in a case wherem is an odd number larger than N/2, an amplifying circuit of the “m”thstage is disposed at the “m”th position of the second row in thesemiconductor substrate in a case where m is an even number equal to orless than N/2, and an amplifying circuit of the “m”th stage is disposedat the “N+1−m”th position of the second row in the semiconductorsubstrate in a case where m is an even number larger than N/2.

[0040] Although the present invention has been described based on theembodiments, the present invention is not limited to the above-describedembodiments, but may be modified or changed within the range set forthin claims.

INDUSTRIAL APPLICABILITY

[0041] The semiconductor integrated circuit according to the presentinvention can be used in imaging devices, computers and soon, which usesa ring oscillator circuit for generating multi-phase clock signalshaving phase difference of equal intervals.

1. A semiconductor integrated circuit, comprising: N-stage amplifyingcircuits, where n is a natural number, connected in a form of a ring toperform oscillating operation, said n-stage amplifying circuits beingarranged in a semiconductor substrate to be divided into a plurality ofrows, wherein in each row an amplifying circuit of “m−1”th stage and anamplifying circuit of “m”th stage are not adjacent to each other, wherem is an arbitrary integer number within a range from 2 to n; and aplurality of wirings for respectively leading out a plurality of outputsignals from said amplifying circuits disposed in one of said pluralityof rows:
 2. A semiconductor integrated circuit according to claim 1,wherein said N-stage amplifying circuits are arranged in thesemiconductor substrate to be divided into two rows, and an amplifyingcircuit of “2i−1”th stage is disposed in a first row and an amplifyingcircuit of “2i”th stage is disposed in a second row, where i=1, 2, . . .N/2.
 3. A semiconductor integrated circuit according to claim 1, wherem=1, 2, . . . , and N, wherein: an amplifying circuit of “m”th stage isdisposed at “m”th position of a first row in the semiconductor substratein a case where m is an odd number not larger than N/2; an amplifyingcircuit of the “m”th stage is disposed at “N+1−m”th position of thefirst row in the semiconductor substrate in a case where m is an oddnumber larger than N/2; an amplifying circuit of the “m”th stage isdisposed at the “m”th position of a second row in the semiconductorsubstrate in a case where “m” is an even number not larger than N/2; andan amplifying circuit of the “m”th stage is disposed at the “N+1−m” thposition of the second row in the semiconductor substrate in a casewhere “m” is an even number larger than N/2.
 4. A semiconductorintegrated circuit according to claim 1, wherein each of said N-stageamplifying circuits supplies differential signals, which are obtained byamplifying a difference between a signal applied to a non-invertinginput and a signal applied to an inverting input, to a non-invertingoutput and an inverting output.
 5. A semiconductor integrated circuitaccording to claim 1, wherein a delay time in each of said N-stageamplifying circuits is controlled by either one of a control voltage anda control current.
 6. A semiconductor integrated circuit, comprising:N-stage amplifying circuits connected in a form of a ring to performoscillating operation to output M-phase clock signals having equal phaseintervals, where M and N are natural numbers and M≦N, said N-stageamplifying circuits being arranged in a semiconductor substrate to bedivided into two rows; and M wirings for respectively leading outM-phase clock signals from said amplifying circuits disposed in one ofsaid two rows. 7 A semiconductor integrated circuit according to claim6, wherein M and N are even numbers.
 8. A semiconductor integratedcircuit according to claim 6, wherein M is equal to N.
 9. Asemiconductor integrated circuit according to claim 6, where i=1, 2, . .. , and N/2, wherein: an amplifying circuit of “2i−1”th stage isdisposed in a first row; and an amplifying circuit of “2i”th stage isdisposed in a second row.
 10. A semiconductor integrated circuitaccording to claim 6, where m=1, 2, . . . , and N, wherein: anamplifying circuit of “m”th stage is disposed at “m”th position of afirst row in the semiconductor substrate in a case where m is an oddnumber not larger than N/2; an amplifying circuit of the “m”th stage isdisposed at “N+1−m”th position of the first row in the semiconductorsubstrate in a case where m is an odd number larger than N/2; anamplifying circuit of the “m”th stage is disposed at the “m”th positionof a second row in the semiconductor substrate in a case where m is aneven number not larger than N/2; and an amplifying circuit of the “m”thstage is disposed at the “N+1−m”th position of the second row in thesemiconductor substrate in a case where m is an even number larger thanN/2.
 11. A semiconductor integrated circuit according to claim 6,wherein each of said N-stage amplifying circuits supplies differentialsignals, which are obtained by amplifying a difference between a signalapplied to a non-inverting input and a signal applied to an invertinginput, to a non-inverting output and an inverting output.
 12. Asemiconductor integrated circuit according to claim 6, wherein a delaytime in each of said N-stage amplifying circuits is controlled by eitherone of a control voltage and a control current.